Hi,
Which FPGA are you talking about?
Klaus
The PLL/MMCM inside the Arty board is capable of min 10Mz o/p or more. ads-ee/FvM have also pointed that out.
This was the reason why it was asked to him the source of this 2MHz clk and to it there has been no info from the OP.
If you have a higher frequency clock available, a digital PLL can generate the 4 MHz clock, however limited to the time resolution of the system clock. Ultimately, you can phase lock an auxiliary high frequency clock to the 2 MHz input, using MMCM dynamic phase shift feature and some user logic.
A bit more complex. You'll design a kind of software PLL with 2 and 4 MHz output, locked to the 2 MHz reference. Dynamic phase shift might be used if the phase jitter requirements are very strict. More likely you'll just oversample the 2 MHz input with a sufficient fast system clock.So if i understand correctly, you want to say that i have 2 MHz clock , I should generate 4 MHz clock from clocking wizard/PLL/MMCM and than synchronize them using MMCM dynamic phase shift feature.
Do you mind to sketch what the input data is and how the 2 MHz clock is "recovered"?The 2 Mhz clock is generated from the input data using the clock recovery algorithm.
Do you mind to sketch what the input data is and how the 2 MHz clock is "recovered"?
The xapp868 design is a digital PLL that can easily generate 4 MHz along with the 2 MHz output.
See how 2 MHz clock is derived from DDS MSB phase[31]. You can generate 4 MHz in a similar way by utilizing phase[30] too.
I was referring to xapp868 where a 32 bit DDS is running at 2.048 MHz. Not sure how your design is different. What's the DDS phase accumulator frequency in your design?
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