Jul 7, 2006 #1 S somchoke Newbie level 3 Joined Jan 1, 2006 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,303 can any one tell me how to generate 4-bit counter usinging only clock and reset in verilog
Jul 7, 2006 #2 P PitBull Newbie level 5 Joined Jun 22, 2004 Messages 9 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 76 Re: 4-bit counter I don't know verilog but asynchronous counter using JK FF shouldn't be too hard. Use 4 JK FF, all inputs 1. Clk0 <= Clock Clk1 <= Q0 Clk2 <= Q1 Clk3 <= Q2
Re: 4-bit counter I don't know verilog but asynchronous counter using JK FF shouldn't be too hard. Use 4 JK FF, all inputs 1. Clk0 <= Clock Clk1 <= Q0 Clk2 <= Q1 Clk3 <= Q2
Jul 8, 2006 #3 kib Advanced Member level 4 Joined Mar 27, 2003 Messages 111 Helped 10 Reputation 22 Reaction score 2 Trophy points 1,298 Location Bangalore, India Activity points 611 Re: 4-bit counter here u go Code: always @(posedge clock or posedge reset) begin if(reset) begin count <= 4'h0; end else begin count <= count + 4'h1; end end
Re: 4-bit counter here u go Code: always @(posedge clock or posedge reset) begin if(reset) begin count <= 4'h0; end else begin count <= count + 4'h1; end end
Jul 8, 2006 #4 R ravurig Junior Member level 2 Joined Jun 21, 2004 Messages 23 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,283 Activity points 129 Re: 4-bit counter always @(posedge CLK or negedge RST) begin if(!RST) COUNT <= 4'd0; else COUNT <= n_COUNT; end assign n_COUNT = COUNT + 'd1;
Re: 4-bit counter always @(posedge CLK or negedge RST) begin if(!RST) COUNT <= 4'd0; else COUNT <= n_COUNT; end assign n_COUNT = COUNT + 'd1;
Jul 21, 2006 #5 eelinker Full Member level 5 Joined Feb 12, 2006 Messages 267 Helped 16 Reputation 32 Reaction score 8 Trophy points 1,298 Location PERSIA Activity points 2,775 4-bit counter In the name of God module counter4(clk, reset, out); input clk,reset; output [3:0] out; reg [3:0] out; always @ (posedge clk or negedge reset) if(!reset) out <= 4'd0; else out <= out+1; endmodule
4-bit counter In the name of God module counter4(clk, reset, out); input clk,reset; output [3:0] out; reg [3:0] out; always @ (posedge clk or negedge reset) if(!reset) out <= 4'd0; else out <= out+1; endmodule