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How to generate 4-bit counter in Verilog using only clock and reset?

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somchoke

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can any one tell me how to generate 4-bit counter usinging only clock and reset in verilog
 

PitBull

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Re: 4-bit counter

I don't know verilog but asynchronous counter using JK FF shouldn't be too hard.
Use 4 JK FF, all inputs 1.
Clk0 <= Clock
Clk1 <= Q0
Clk2 <= Q1
Clk3 <= Q2
 

kib

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Re: 4-bit counter

here u go
Code:
always @(posedge clock or posedge reset)
begin
  if(reset)
  begin
    count <= 4'h0;
  end
  else
  begin
    count <= count + 4'h1;
  end
end
 

ravurig

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Re: 4-bit counter

always @(posedge CLK or negedge RST) begin
if(!RST) COUNT <= 4'd0;
else COUNT <= n_COUNT;
end

assign n_COUNT = COUNT + 'd1;
 

eelinker

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4-bit counter

In the name of God

module counter4(clk, reset, out);
input clk,reset;
output [3:0] out;
reg [3:0] out;

always @ (posedge clk or negedge reset)
if(!reset) out <= 4'd0;
else out <= out+1;

endmodule
 

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