How to fix setup time violation after synthesis?

[onion2014]

is there any step after synthesis can fix this problem? can i guide the P&R to have some usefull clock skew for that?

 

[rca]

Re: how to fix setup time violation after synthesis, don't lower the operating freque

First the setup must be met after the synthesis.
You could constraints the synthesis with higher frequency, to force it to choose better architecture for speed, and then relax the setup constraint during the PnR.
To obtain a better synthesis you could also used the synthesis with physical or topological information, which help to estimate the net delay.
During the synthesis, after placement you shouldhave the setup met, with a optimization design phase, and so on after CTS and after routing, and for si mode as well.

 

[zjushmily]

Re: how to fix setup time violation after synthesis, don't lower the operating freque

many ways to fix setup violation after synthesis.
1. size cell and minimize data path delay.
2. check hold margin and useful skew.
3. use LVT cell
if all ways can not work. you 'd better add more margin to re-synthesis or re-design.

 

[karan1207]

Re: how to fix setup time violation after synthesis, don't lower the operating freque

Well, if you do not want to change the device, then you can apply forward bias on the Body/substrate terminal of the transistor.

 

[englishdogg]

Re: how to fix setup time violation after synthesis, don't lower the operating freque

Well all the above are correct, but to add my order of applying these would vary depending on the observation / debug/ finding

First review timing report, check if all constraints are correct. Review delay of each cell in the timing path. See if optimization is done well in terms of reducing levels of logic, using complex cells, upzising of libcells. If all OK then see if Leaky cells are used or not.

Adding margin during synthesis is a very common process but really not a very good idea. I have myself seen industry experts using atleast 25-28% of pessimism during synthesis in order to meet timing. Well as it does help, but by doing so we tend to over contrain the paths that we easily close as well which is almost 70% of the design; your violations would be 30 or less than 30%. If you over constraining is focussed on these 30% paths then it makes sense not otherwise.
Before over constraining i would also try ungroup, creating more cost groups etc

Biasing would occur in the later part of the flow.

hope this helps. cheers!!

 

[ivlsi]

Could you give more info about using different cost groups? How may it help?

 

[rca]

create a cost group which included path flop-to-flop, input-to-flop, flop-to-output, input-to-output, and define a weight important for the flop-to-flop.

 

[ivlsi]

create a cost group which included path flop-to-flop, input-to-flop, flop-to-output, input-to-output

So, a single cost group for all these paths?

define a weight important for the flop-to-flop

should weight numbers be defined only for these paths? why not for others as well?
what weight numbers are most acceptable? how do they work? Could you please provide an example how to define them? Do they work for DC as well as for RC?

 

[rca]

sorry no, a cost group for all the group I define before.

 

[ivlsi]

You could constraints the synthesis ... to choose better architecture for speed

What do you exactly mean? Flattening the design? Are there another constraints to improve the implementation architecture?

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can I define different efforts on different cost groups?

Will the tool work on the different cost groups separately?

 

[rahul.achates]

it's depend , how much is setup violation ..

if setup violation is large , then it's better to fix it in design by updating architecture.

if setup time violation is not too high ... one can look in clock skew and ask PD team if they can fix it or not .. they can fix it using LVT cells which are fast cells but power leakage will be high.

Also you need to find out how much margin you have given and which library you are using .. some library has own setup/hold margin and if you have given from SDC file then it will be double setup margin and may result in violation.

check report thoroughly and identify what causes setup violation ..

Rahul

 

[layowblue]

Re: how to fix setup time violation after synthesis, don't lower the operating freque

Hi, karan1207

Could you elaborate a bit on how forward biasing helps on setup timing closure? How much freedom do you get usually in digital P&R for this method?

Thanks

Well, if you do not want to change the device, then you can apply forward bias on the Body/substrate terminal of the transistor.

 

[ivlsi]

How do you create cost groups? could you please provide an example (including syntax)?

 

[englishdogg]

I think now is the good time to look at the product documentation .. for syntactical help
IT will vary from product to product