Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to fix setup and hold violations?

Status
Not open for further replies.

jaseel_abdulla

Newbie level 4
Joined
Aug 13, 2007
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,326
Hi Seniors

Suppose in a design there are set up and hold violations.

which one should be fixed first and why.

Is fixing both is important. how can we fix them??

Please help me......Plz share your thoughts.


Thanks in advance
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
Re: Violation question!!

Fixing both are important. You may fix either one before the other. But just remember one thing a chip violating hold, is of no use, where as if there is a setup violation in a chip, then you may be able to make it work by reducing the freq of operation
Kr,
Avi
http://www.vlsiip.com
 

jaseel_abdulla

Newbie level 4
Joined
Aug 13, 2007
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,326
Re: Violation question!!

Thank you sir.

Can you tell me, how to fix hold time violation.

Other than reducing frequency, is there any method to avoid setup violation.

Thanks
 

shavakmm

Member level 4
Joined
Oct 6, 2007
Messages
75
Helped
9
Reputation
18
Reaction score
6
Trophy points
1,288
Location
Bangalore
Activity points
1,707
Re: Violation question!!

All VLSI engineers scratch their head to eliminate setup and hold violation... different methods and optimization steps are there in different steps of VLSI IC design flow to counteract setup and hold violations.... please search within edaboard.com ...u can find several discussions.

http://asic-soc.blogspot.com
 

au_sun

Full Member level 2
Joined
Aug 5, 2004
Messages
147
Helped
15
Reputation
30
Reaction score
4
Trophy points
1,298
Activity points
1,184
Violation question!!

For fixing Hold violation between two registers,
various techniques are there,
1. try to add delays cells in between the registers without violation setup timing
2. try to utlize usefull skew in the clock paths betwwen two registers.
etc..

for Fixing setup,
1. try to optimize data path between two registers, without violation hold timing
2. try to fix the transition violation in the data path.
3. swapping low driving cells with high driving cells.
etc....

all the above techniques can be used based upon the suitable conditions, without creating further violations
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top