the question posed to me is, how to fix setup violation ? my answer is to reduce the combinational path delay sitting in between Lflop and Cflop.
the next question is, how you do that ? my answer is, By registering the data available at certain point in the combinational logic.
the next question is, Then how you address this, if it is a pure combinational block.? while im thinking, she said, have you not seen any net-to-net timing path in your reports ?
Then i thought that , discussion went from reg2reg portion to port-to-port .
I presented everything i encountered. I want some light on this. I am confused what she was trying to get from me ??