How to find forbidden states in a digital circuits?

[venn_ng]

Let's say I have 6 valid states for the circuit shown below. Since I have 4 latches, I could possible have 16 possible states. Is there a technique to find out if I start with one of those 10 (16-6) invalid states, can I enter the valid state or will I be stuck in those invalid states? (other than manually verifying it starting with each of those invalid states)

 

[dick_freebird]

By inspection / manually is the only way I've
ever known. Other than letting some testability
/ synthesis tool report fault coverage, maybe after
letting it try to make a vector-set. But it's been
decades since I last had to make deep vector
sets for digital parts and design-tool technology
may have something new to offer?

6 valid states out of 16, says you probably want
some logic minimization?

Depending on which codes are valid and not,
you might find it useful to create a "bogus_det"
logic to apply over this block, sniffing for invalid
states and forcing a return to valid. If it's a counter
(by design or by larger-loop behavior) then it
might be that what you have is two "tracks"
that individually will loop but never meet, in
such a case the "bogus_det" could be very
simple (only needing to catch one of the N
bad codes).

This kind of analysis is important to systems
like spacecraft, where heavy ions or even
protons / neutrons can flip a bit and transport
you to "the other side" of a bifurcated (valid
and invalid state-domains present) logic. It
wants proved that either (a) there are no such
dead-end states or state-groupd or (b) for
every invalid state there is an orderly, no-
external-intervention process that will clear
them and return to valid operation.

 

[ads-ee]

To elaborate further on the previous post, depending on the optimizations done by a synthesis tool you could end up with some invalid state values that eventually return to the valid state-domain or loop in an invalid state-domain. This is entirely dependent on how the invalid state transitions are optimized by the tools.

There may be tools, other than a netlist simulation, that can check this but I haven't worked with ASIC tools for over a decade. Some of the ways you can guarantee that the invalid states can reach a valid state is to:
a. have the invalid state transitions defined
b. detect invalid states like the previous post suggests
c. use a synthesis tools safe state machine switch (if there is one).

All of these restrict the way synthesis can optimize the state machine and forces the compiler to implement the invalid states so they will eventually return to a valid state.

 

[ThisIsNotSam]

well, there is a reason why design practices are to enforce the use of reset flip-flops. you go into a known state, always.

 

[venn_ng]

well, there is a reason why design practices are to enforce the use of reset flip-flops. you go into a known state, always.

The only catch is you have to synchronize reset with the input clk otherwise it can still go metastable and enter some weird state again

 

[FvM]

In addition to the mentioned reset problem, expect that a FSM reading asynchronous input signals can transit to any illegal state.

 

[ThisIsNotSam]

The only catch is you have to synchronize reset with the input clk otherwise it can still go metastable and enter some weird state again

which is, 99 out 100 times, trivial to achieve.