KlausST
Advanced Member level 7
Hi,
Is fg frequency sync'd to sample frequency of adc?
It seems to me you are mixing up a lot of test steps in your description. Changing channels, voltage and duty cycle within one test step makes no sense. You need fixed values to get a reliable result.
I really try to find out exactely at wich point of test you think you need a fir filter and what you think you gain with it.
Usually there should be a test engineer, who determines the test steps, test conditions and the pass/fail limits.
Is it possible for you to talk to this man? Maybe he can say what filters you need.
*********
Usually for one test step you have fixed and known input conditions.
A description to this could be: square wave 10.00MHz, 0.50V, 3.00V, 25% duty cycle, synced to adc sample frequency, Ch1
Then you need to take a known count of adc samples with a fixed sampling frequency, lets say 50.00MHz.
Then you need to process these data.
Lets say on: low level, high level, maybe others
( with the given input signal it makes no sense to process on: noise, duty cycle, distortion, RMS... the results won't be reliable)
Then there could be the next test step wih 50% duty cycle for example.
Then there could be the next test step wih 25% duty cycle for example but on Ch2.
And so on...
Klaus
I don't understand..
Is fg frequency sync'd to sample frequency of adc?
It seems to me you are mixing up a lot of test steps in your description. Changing channels, voltage and duty cycle within one test step makes no sense. You need fixed values to get a reliable result.
I really try to find out exactely at wich point of test you think you need a fir filter and what you think you gain with it.
Usually there should be a test engineer, who determines the test steps, test conditions and the pass/fail limits.
Is it possible for you to talk to this man? Maybe he can say what filters you need.
*********
Usually for one test step you have fixed and known input conditions.
A description to this could be: square wave 10.00MHz, 0.50V, 3.00V, 25% duty cycle, synced to adc sample frequency, Ch1
Then you need to take a known count of adc samples with a fixed sampling frequency, lets say 50.00MHz.
Then you need to process these data.
Lets say on: low level, high level, maybe others
( with the given input signal it makes no sense to process on: noise, duty cycle, distortion, RMS... the results won't be reliable)
Then there could be the next test step wih 50% duty cycle for example.
Then there could be the next test step wih 25% duty cycle for example but on Ch2.
And so on...
Klaus