in a module, how to find all combinatorial path from inputs to outputs, i think that write a scripts can do it. i don't know how to write? somebody help me?
If you mean how synthesis tools do it, You should check any paths from inputs to outputs which do not pass through your clocked always block in Verilog (process block in VHDL).
I means that in my design, there are some paths that are combinatorial paths from input port to output port, i need a script to find all these combinatorial paths.
I know that using "report_timing -from <input port> -to <output port> can report directly,but now in my design, there are hundreds of port, So i wan to write a scripts to identify these combinatorial paths.
who can help me?