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from modesim user manual
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A VCD file from source to output
The following example shows the VHDL source, a set of simulator commands, and the resulting VCD output.
VHDL source code
The design is a simple shifter device represented by the following VHDL source code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SHIFTER_MOD is
port (CLK, RESET, data_in : IN STD_LOGIC;
Q : INOUT STD_LOGIC_VECTOR(8 downto 0));
END SHIFTER_MOD ;
architecture RTL of SHIFTER_MOD is
begin
process (CLK,RESET)
begin
if (RESET = '1') then
Q <= (others => '0') ;
elsif (CLK'event and CLK = '1') then
Q <= Q(Q'left - 1 downto 0) & data_in ;
end if ;
end process ;
end ;
VCD simulator commands
At simulator time zero, the designer executes the following commands:
vcd file output.vcd
vcd add -r *
force reset 1 0
force data_in 0 0
force clk 0 0
run 100
force clk 1 0, 0 50 -repeat 100
run 100
vcd off
force reset 0 0
force data_in 1 0
run 100
vcd on
run 850
force reset 1 0
run 50
vcd checkpoint
quit -sim