victordion
Newbie level 6

Hello guys. I recently need to design a circuit (no need for fabrication but need to make it technologically practical) which has the capability of outputing constant voltage pulses. The amplitude and width of the pulses should be controllable.
I am considering using DAC, however because I am not an analog IC designer there are several issues that I am not very sure about.
Q1. How to estimate the power consumption of the DAC in the my proposed scenario? I guess a datasheet generally specifies the power of a DAC at the state of outputing a steady sinusoidal signal, and the power is approximately propoertional to the sampling frequency. However in my scenario, the DAC does not work in continuous mode, rather, it may output a 10ns pulse every 100ns (I call it step response mode). How do I model the power consumption then?
Q2. Does the DAC power specified on datasheet usually include the power consumed by its load? I see some datasheet saying the DAC can output up to 5mA current, is this (5mA * R_load) power considered as part of DAC consumed power?
Q3. What is the typical settling time of a DAC? Is it related to the sampling frequency? For example for a DAC capable of working at 1GHz, how long does it usually take to get a 95% close output voltage after the input is applied? (And besides, what is a typical settling time of an 1GHz ADC working in step response mode?)
Q4. Consider about state-of-the-art situation, for an 8-bit 1GHz DAC, what is the best power performance nowadays?
Any help is appreciated!
I am considering using DAC, however because I am not an analog IC designer there are several issues that I am not very sure about.
Q1. How to estimate the power consumption of the DAC in the my proposed scenario? I guess a datasheet generally specifies the power of a DAC at the state of outputing a steady sinusoidal signal, and the power is approximately propoertional to the sampling frequency. However in my scenario, the DAC does not work in continuous mode, rather, it may output a 10ns pulse every 100ns (I call it step response mode). How do I model the power consumption then?
Q2. Does the DAC power specified on datasheet usually include the power consumed by its load? I see some datasheet saying the DAC can output up to 5mA current, is this (5mA * R_load) power considered as part of DAC consumed power?
Q3. What is the typical settling time of a DAC? Is it related to the sampling frequency? For example for a DAC capable of working at 1GHz, how long does it usually take to get a 95% close output voltage after the input is applied? (And besides, what is a typical settling time of an 1GHz ADC working in step response mode?)
Q4. Consider about state-of-the-art situation, for an 8-bit 1GHz DAC, what is the best power performance nowadays?
Any help is appreciated!