In the design of single loop 3 ordersc sigma delta modulator ,how to eliminate the 1/f noise of the first intergator beside the chopper theck ?
Also ,due to the suppress of the noise tranfer founction in low frequency , the cap of second and third integrator can be very small, but how to deside the lowest value of the cap size?
what's the influence of the opa's offset of the first intergrator?
1/f noise in the first integrator can be reduced by using Pmos inputs and also making them very large! Of course this creates a large input cap and it should be taken into account for stability.
As for the caps. You need to have scaling coefficients for you modulator. These coefficients determine your cap size and input resistance (example for continuous time). Then you can scale the caps up or down which would make your resistance go down or up ( opposite). You then just make it so your resistance thermal noise does not effect your performance!
As for the offset of the first integrator, it does not effect your modulator as long as your inputs stay in saturation.
Hope this helps
Jgk