HOw to dump fsdb file in modelsim?

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jamesyang1209

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modelsim fsdb

Dear Group,

I am using modelsim for simulation. I can dump fsdb file (for debussy) by writing some statement in verilog code. But I don't know how to write a stement to do that in VHDL code. Please tell me.

Thanks in advance.
 

fsdb file

Hi,

I think u are not using the modelsim pli properly. Here is the procedure how to do it.

in the list of VHDL files, first compile novas.vhd from u'r /share/PLI/modelsimfli/novas.vhd file

then in the top level module (test bench) use this line and also the set of commands.

use work.novas.all

process
begin
fsdbDumpfile("vhdl.fsdb");
fsdbDumpvars(0,"top level module name"); ##this line is important and the scope is also important in the VHDL design.
end process;


Now it will work fine

Regards,
Ganesh
 

fsdb dump

I have tried copy novas.vhd to modelsim project directory, and then compile it. No error ocour.
But, after I add "use work.novas.all;" in my test bench one error occour:
"'novas' is not a library or a package." Then I change to "use work.pkg.all;" since one package call pkg in novas.vhd.
Compile testbench, error pass.

After that, I add follows within architecture of the test_top
process
begin
fsdbDumpfile("vhdl.fsdb");
fsdbDumpvars(0,"test_top");
end process;

Then run simulation, message "test_top had been traversed" is displayed all the time and simulation time didn't increase.
vhdl.fsdb has been dump, but only time 0 (time didn't increase).
Why?
And, should I add "-pli novas.dll" in simlation options?
 

fsdbdumpfile

that is because the novas.vhd you used is wrong
i just do as cganeshprabhu said too, it cannot work
now i found why
you should use
$debusy_inst/share/PLI/scirocco/$platform/novas.vhd
sorry it is too old
 

fsdb modelsim

Hi,
You are missing a wait inside the VHDL process, do:

Code: 
process 
begin 
fsdbDumpfile("vhdl.fsdb");
fsdbDumpvars(0,"test_top");
[b]wait;[/b] -- You missed this!!
end process;

HTH
Ajeetha, CVC
www.noveldv.com
 

modelsim dump fsdb

hi, now i meet one question,pls help me!
in my desing,top module is verilog ,down module have vhdl module,how should i dump fsdb file in modelsim?
 

modelsim fsdbdumpfile

i have tried,it's ok!Tks for ljxpjpjljx!!!
 

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