How to drive a transistor into saturation in cadence (if its in triode)?

[sutapanaki]

Thanks LvW,
That's exactly what I was trying to explain here too but it didn't stick for some reason. Yes, there are few discussions on the topic in which both you and I participated before. Evidently, there is a need for more of them.

 

[jony130]

In this context it is to be noted that - because of historical reasons - there are two different saturation region definitions for the BJT and the FET.

When I start learning about BJT and FET I notice the big difference between saturation in FET and in BJT.
The saturation for the FET's transistor is what we describe in BJT as a "active-region".
LvW do you have any info what are those "historical reasons" for such a big difference?

 

[sutapanaki]

I'm not quite sure about this but I think in bjt they saturate the base with carriers, since both junctions are forward biased. Maybe in MOS, it is called saturation because the current saturates when mos transistor works as a current source. But I could be wrong if memory doesn't serve me right. LvW can probably add more.

 

[LvW]

Yes, I think sutapanaki got the point.
One should ask: Who resp. what parameter is "saturated" (that means: does not rise any more - or only negligible)?

 

[erikl]

One should ask: Who resp. what parameter is "saturated" (that means: does not rise any more - or only negligible)?

... doesn't fall any more -- or just unessentially -- in case of the BJT saturation voltage Vce .

 

[babaduredi]

Hi Khisha,
As the setup given in your circuit, you can not have both P1 and N2 in saturation, since P1 is in saturation with gate connected to gnd!, it's drain voltage must be less than or = Vtp. Now this much low drain voltage prevents N2 to go in saturation, for which you need high drain voltage of magnitude more than VgN2DC-Vtn.
To drive both in saturation, one option is to reduce DC component of gate input of N2. You can try different w/l for pmos current mirror but here also you need to monitor operation region of P1. As far as this circuit is concerned, i don't think without adding additional feedback circuitry it's good to drive both in saturation.

 

[sutapanaki]

Do you really, honestly believe what you said is correct? How about gate of P1 being at vdd-Vtp and drain at vdd/2? There is a good chance that both transistors are in saturation. Why do you think that the gate of P1 should be at gnd? In this circuit, what is important is not so much the gate voltage of P1 but the drain voltage (of both P1 and N1). Problem is that there is no control over the drain voltage in the circuit as it is shown.

 

[babaduredi]

Hi sutapanki,
You are right. Thanks for correcting me. I just got to that conclusion by assuming voltage drop across the current source as zero but it was a mistake. A current source can have any voltage across it depending on situation. Thanks again.