Basic sigma-delta ADCs like that shown in Lattice paper can be often found in simple FPGA evaluation boards. You should also find code examples for it.
For a systematical design, you can refer to SD literature. A specific point of the shown circuit is that a LVDS receiver is used as analog comparator, although it's not specified for this operation. For this reason it's impossible to predict the analog performance.
In the context of this thread about analog signal processing for beamforming, a SD-ADC with maximum 50 kHz bandwidth is simply off-topic.