OBUF_LVDS
OBUFT_LVDS IBUF_LVDS
...
module top (A_p, A_n);
input A_p, A_n;
wire Aout;
IBUFDS_LVDS_25 ibuf1 (.I(A_p), .IB(A_n), .O(Aout));
...
endmodule
IBUFDS_LVDS_25 ibuf1 (.I(A_p), .IB(A_n), .O(Aout));
May I do just do this!
always @(posedge Aout ) // identify Aout 's rising edge
begin // regard Aout as conversion of A_p and A_n
DATA_OUT <=DATA_IN ;
................................
end
Can you help me to explain this , they are LVDS why it just have one Input or Output !can you give some material for study ! whether (OBUF_LVDS OBUFT_LVDS IBUF_LVDS) and (IBUFDS_LVDS_25 OBUFDS_LVDS_25) have some differences ? I just see IBUFDS_LVDS_25 in VirtexII pro user manual but my device is spartan2e so two types primitive confuse me !Verilog example
This example contains LVDS input, output, and bidirectional I/O.
module LVDSIOinst (CLK, DATA, Tin, IODATA_p, IODATA_n, Q_p, Q_n) ;
input CLK, DATA, Tin;
inout IODATA_p, IODATA_n;
output Q_p, Q_n;
wire iodata_in;
wire iodata_n_out;
wire iodata_out;
wire DATA_int;
reg Q_p_int;
wire Q_n_int;
wire CLK_int;
wire CLK_ibufgout;
wire Tin_int;
IBUF_LVDS UI1 ( .I(DATA), .O( DATA_int));
IOBUF_LVDS UIO_p ( .I(iodata_out), .T(Tin_int), .IO(IODATA_p),
IBUF_LVDS UI2 (.I(Tin), .O (Tin_int));
OBUF_LVDS UO_p ( .I(Q_p_int), .O(Q_p));
OBUF_LVDS UO_n ( .I(Q_n_int), .O(Q_n));
.O (iodata_in));
IOBUF_LVDS UIO_n ( .I (iodata_n_out), .T(Tin_int), .IO(IODATA_n),
.O ());
INV UINV ( .I(iodata_out), .O(iodata_n_out));
IBUFG_LVDS UIBUFG ( .I(CLK), .O(CLK_ibufgout));
BUFG UBUFG (.I(CLK_ibufgout), .O(CLK_int));
always @ (posedge CLK_int)
begin
Q_p_int <= DATA_int;
end
assign iodata_out = DATA_int && iodata_in;
assign Q_n_int = ~Q_p_int;
endmodule
jay_ec_engg said:Hi friends...
How can I do single endded to differential and differential to signale ended conversion with FPGAs ??
i.e. Can I do LVDS to LVTTL conversion and LVTTL to LVDS conversion with FPGAs??? any xlinx FPGA has this inbuil support ???
jay_ec_engg said:Hi friends...
How can I do single endded to differential and differential to signale ended conversion with FPGAs ??
i.e. Can I do LVDS to LVTTL conversion and LVTTL to LVDS conversion with FPGAs??? any xlinx FPGA has this inbuil support ???
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