always@smart
Full Member level 4
clock devider
Hi all,
I gonna use clock devided by 2 in my design. can anyone here tell me that:
1. should i just use a register to get clock-divided-by-2 or on-chip PLL!!??
2. what are the protential problem of using two clocks in a design when doing synthesis!!??
thank you in advance
regards,
always@smart
Hi all,
I gonna use clock devided by 2 in my design. can anyone here tell me that:
1. should i just use a register to get clock-divided-by-2 or on-chip PLL!!??
2. what are the protential problem of using two clocks in a design when doing synthesis!!??
thank you in advance
regards,
always@smart