When working with Xilinx FPGAs, it's a good idea to review Xilinx documents (user guides, application notes) when referring to specific features, e.g. DCM.
In a more general view, you should consider how exact the said clock frequencies can be met, respectively what you require. You'll notice that 18 kHz frequency can be achieved exactly, when using x9 PLL frequency multiplication (a more complex function than basic DCM) and 44.24 kHz can't be met exactly. You have to accept either a frequency deviation or some jitter with a fractional divider. Because you didn't tell any performance requirements, I won't elaborate on possible solutions. They are general knowledge in the FPGA world anyway, I suppose.