How to display ASCII state when simulating one-hot encoding FSM ?

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I implemented a one-hot FSM using the systemverilog "enum" type as suggested in this page : https://www.verilogpro.com/systemverilog-one-hot-state-machine/
And I used "reverse case statement" as declared in that page.

But in Simvision the state can't be displayed as ASCII. In the waveform, state[:] is shown as binary code.
Do you know how to resolved that?
 

State is declared as logic [3:0], not ASCII. You happened to use parameters with human readable names to define it but that doesn't make it ASCII.

You'd need to explicitly code your own mux or if/then/else statement to assign a string the name of your state based on the value state if you want to see strings in simulation.

Particularly with 1-hot why bother?
 


you can create mnemonics in the simulation environment, regardless of how you coded the states. it's handy.
 

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