[SOLVED] How to display a image on PC using FPGA FROM BRAM?

[gmk3]

Heya everyone..
I have stored the image in BRAM by .coe file now, i just want to read the stored data from BRAM and display it on PC using VERTEX ML403,

i have verilog code where i am reading the image from stored bram.

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Code Verilog - [expand]
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module readimage(clka,clkb,addrb,addra,wea,dina,doutb);
input  clka,clkb;
input [15:0] addra,addrb;
input [7:0] dina;
output [7:0] doutb;  
reg [7:0]memory[55680:0]; 
input wea;
reg [7:0]doutb;
reg [7:0]pipe;
 
imgmem mem (
  .clka(clka), // input clka
  .wea(wea), // input [0 : 0] wea
  .addra(addra), // input [15 : 0] addra
  .dina(dina), // input [7 : 0] dina
  .clkb(clkb), // input clkb
  .addrb(addrb), // input [15 : 0] addrb
  .doutb(doutb) // output [7 : 0] doutb
);
 
always @ (posedge clka)
begin
if(wea)
memory[addra] <= dina;
else 
pipe <= memory[addra];
 
doutb <= pipe;
end
endmodule

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Can i know the steps from my code to the output on the PC.

Please help me.

Thankyou in advance.

 

[TrickyDicky]

You'll need some form of communcation - probably easiest would be an RS232 serial core. They are quite simple and there are plenty of examples out on the internet.

 

[gmk3]

Hie TrickyDicky

Thanks for the suggestion, can you please tell me if i am writing the code correctly. and how to get the output using VGA.

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Code Verilog - [expand]
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module readimage(clka,addra,douta);
input  clka;
input   [15:0] addra;
output [7:0] douta;  
reg [7:0] memory[55680:0]; 
reg [7:0] douta1;
reg [7:0] a;
 
 
mem bram (
  .clka(clka), // input clka
  .addra(addra), // input [15 : 0] addra
  .douta(douta) // output [7 : 0] douta
);
 
 
always @ (posedge clka)
begin
memory[addra] <= a[addra];
douta1 <= memory[addra] ;
end
assign douta= douta1;
endmodule

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and i am getting error..

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Code dot - [expand]
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:Xst:528 - Multi-source in Unit <readimage> on signal <douta<7>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal <douta<6>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal <douta<5>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal <douta<4>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal <douta<2>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal <douta<1>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal <douta<0>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <readimage> on signal < 
   Output signal of MUXF5 instance <bram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux1_f5>
   Output signal of FD instance <douta1_0>

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Thanks in advance.

 

[ads-ee]

Why are you both trying to infer a memory (the always blocks in posts #1 & #3) and instantiate a memory. You have two drivers on the output douta (i.e. one from the always block and one from the instance bram.

I also don't get you second code I've never seen a memory in an FPGA that allows for no write enable? Your code in post 1 with the exception of the both an attempt to infer memory and instantiate the same memory aside is closer to being usable than the code in post #3.

You need to read a Verilog book and go online and read some of the Verilog tutorials. I don't think you know anything about instantiating a module and what that really means. (FYI, it's like sticking ICs on a breadboard and soldering wires to connect them to other ICs).

 

[gmk3]

Heya ads-ee

Thanks for your advice. i am learing verilog, and trying to learn do code.
I guess instead of criticizing help in a positive way would be appreciated.

Thankyou once again. I am learning from my mistakes...