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how to disable scan chain in dc shell

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eda_wiz

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what is scan insertion

hi all,
can anyone explain , what is scan insertion ? How is it different from boudayr scan (JTAG)..

thanks
 

Ace-X

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Hi!

Here is quite definitive description of scan design approach from The VLSI Handbook:
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The most popular DFT approach is the scan design. The scan design approach enhances every flip-flop in the circuit with a multiplexing mechanism that allows for the following. In the operation mode, the flip-flop behaves as usual. In the testing mode, all the flip-flops are connected to a single shift chain. The input of this chain is a single controllable point and its output is a single observable point. In the testing mode, each scanned flip-flop is a fully controllable and observable point. Observe that
the testing phase amounts to testing combinational logic. Therefore, the ATPG (or the on-chip TPG) needs to generate single patterns instead of sequences of patterns. Each generated pattern is serially shifted in the scan chain. Typically, this process requires as many clock cycles as the number of flip-flops. Once every flip-flop obtains its controlling value, the circuit is turned to operation mode for a single cycle. Now the flip-flops are disconnected from the scan chain, and at the end of the clock cycle, the flip-flops are loaded with values that are to be observed and analyzed. Now the circuit is switched back into the testing mode (i.e., all flip-flops form again a scan chain). At this point, the states of the flip-flops are shifted out and are analyzed. This requires no more clock cycles than the number of flip-flops. The described scan approach is also called full scan because all flip-flops in the circuit are scanned. The advantage of the full scan approach is that it requires only two additional I/O pins: the input and output of the scan chain, respectively. The disadvantage is that it is time-consuming due to the shift-in and shift-out processes for each applied pattern, especially for circuits with many flip-flops. For such circuits, it is also hardware intensive because every flip-flop must have dual operation mode capability. The hardware and the application time can be reduced by employing CAD tools. Another way to reduce application time and hardware cost is through partial scan. In partial scan, only a subset of flip-flops is scanned. The flip-flops and their ordering in the scan also require sophisti-cated CAD tools. The tradeoff in partial scan is that the ATPG tool may have to generate test sequences rather than single patterns. A CAD tool is needed in order to select and scan a small number of flip-flops. This guarantees low hardware overhead and low application time. The flip-flop selection must also guarantee an upper bound on the length of any generated test sequence. This simplifies the task of the ATPG tool and has an impact on the test application time.
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Hope now it should be clear what is the difference between scan insertion and boundary scan.

Ace-X.
 

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