Self refresh was just a guess, I see that CKE has to be released to activate it, this doesn't happen in Quartus SDRAM IP. Literature suggests however, that SDRAM content of most cells may be retained at low temperatures even for minutes.
You can look into generated files to see how the refresh period is actually changed with IP settings. The SDRAM controller core doc doesn't specify supported refresh cycle settings, but refresh_counter size is 14 bit and value of 0 sets just the maximum cycle of 164 us. To disable refresh completely, you need to manipulate the generated HDL file xxx_sdram.v.