How to difine different propagation delays by using Verilog

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ken_cn

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Hi,
I want to make a nand gate using verilog. It needs contain 3 different propagation delays in 3 different conditions. And it must choose one of the propagation delay according on the condition in simulation.
how can I do?
Thanks!

Ken
 

Re: How to difine different propagation delays by using Veri

Hi ken_cn,

Try this:

##################################################
`timescale 1ps/1ps

module 3_con_nand(
in0,
in1,
con,
out
);

parameter con_0_delay = 1, // You can change this value to you want
con_0_delay = 2,
con_0_delay = 3;

input in0;
input in1;
input [1:0] con;

output out;

always@(con or in0 or in1)
case(con)
2'b00:
out = #con_0_delay ~(in0 & in1);
2'b00:
out = #con_1_delay ~(in0 & in1);
default:
out = #con_2_delay ~(in0 & in1);

endmodule

#############################################
 

Re: How to difine different propagation delays by using Veri

Thank you very much.
 

Re: How to difine different propagation delays by using Veri

Thanks Wadaye.
But this may add one input pin in my symbol. I don't like to change the symbol.
Counld I define "con" as a global variable? Could you help me? Thnak you very much.

Ken
 

Re: How to difine different propagation delays by using Veri

Hi,

Please note that "#delay" can be used only for simulation and not for synthesis
 

Re: How to difine different propagation delays by using Veri

thanks
I only use in simulation.how can I do?
 

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