How to detect the second one in a serial bit stream

[bansalr]

Hi,
I want to detect a second one '1' in a serial bit stream.
Can some one suggest me optimal logic implementation.

 

[snake_eyes]

bansalr,
You will have to sample the serial stream with a clock. Make sure that the sampling clock frequency fulfills the Nyquest's criteria.
You can make a simple state machine to detect any sequence then...
Please give me some more specific info about your problem and we can work towards the solution.

 

[maksya]

Shifting 2-bit register. And if there is "11" in that register then activate detect signal.

 

[lambtron]

I want to detect a second one '1' in a serial bit stream. Can some one suggest me optimal logic implementation.

It depends on whether you have access to the stream's data clock. If so then you can get away with something simple such as the solution hinted at by maksya.

If the data clock is not available then you must implement a state machine as suggested by snake_eyes. In this case, a suitable state machine might implement the following state diagram. Note that some sort of Start trigger is required to begin the detection sequence. Without knowing more about your application it is impossible to say where this start signal will come from.

 

[artem]

this logic will reset counter when second bit is detected and counting will start again . but if you need to keep out high for consequitive '1' then this has to be changed with little modification as maksya said.

library ieee;
use ieee.std_logic_1164.all;

entity parser is
    port(clk : in  std_logic;
         rst : in  std_logic;
         din : in  std_logic;
         dout: out std_logic);
end parser;

architecture parser of parser is
begin
    process(clk, rst)
        variable count : integer range 0 to 2;
    begin
        if(rst = '1') then 
			dout <= '0';
            count := 0;
        elsif (clk'event and clk = '1') then
            if(din = '1') then
                if(count = 1) then
                    dout <= '1';
                    count := 0;
                else
                    dout <= '0';
                    count := 1;
                end if;
            else	   
				count := 0;
                dout <= '0';
            end if;
        end if;
    end process;
end parser;

 

[bansalr]

Actually i wanted to know if we have say 32 bit of data. what is combinational logic
to search for a second one.

 

[maksya]

Actually i wanted to know if we have say 32 bit of data. what is combinational logic
to search for a second one.

Is it critical in your case to use only combinational logic?

 

[bansalr]

Yes, Say we r getting a 32 bit of data or 64 bit of data in a single clock. then we have only a clock period left to do the search.

 

[tukken]

Your SPEC maybe
1. Input 32 bit data
2. Detect if there exist second "1" bit
? 3. Detect the position of second "1" bit

If the timing not very tight, your could use a CSA array to detect it. If the Sum of all 32 bit > 1, then ther must exist second "1" bit.

 

[bansalr]

yes, the probelm is to detect the position of 2nd 1 bit in 32 bits of data

 

[tukken]

1． We consider the 4bit situation and get the truth table
Define,
Input datain [3:0];
Output P2nd [1:0]; //If exist second 1, the position of second 1
Output P1st [1:0]; // the position of first 1
Output exist; //Second 1 exist
Output only1; //Only 1 exist
Truth table,
Datain[3:0]
Datain[3:0] Only1 exist P2nd[1:0] P1st[1:0]
0000 0 0 00 00
0001 1 0 00 00
0010 1 0 01 01
0011 0 1 01 00
0100 1 0 10 10
0101 0 1 10 00
0110 0 1 10 01
0111 0 1 01 00
1000 1 0 11 11
1001 0 1 11 00
1010 0 1 11 01
1011 0 1 01 00
1100 0 1 11 10
1101 0 1 10 00
1110 0 1 10 01
1111 0 1 01 00

2． After the 1st stage, we could get
Exist[7:0];
Only1[7:0]
P2nd0[1:0]; //the first 4 bit, if second 1 exist, the postion of second 1
P2nd1[1:0], P2nd2[1:0], P2nd3[1:0], P2nd4[1:0], P2nd5[1:0], P2nd6[1:0], P2nd7[1:0];
P1st0[1:0]; //the first 4 bit, the postion of first 1
P1st1[1:0], P1st2[1:0], P1st3[1:0], P1st4[1:0], P1st5[1:0], P1st6[1:0], P1st7[1:0];


Always @(Exist[1:0] or Only1[1:0] or P2nd0[1:0] or P2nd1[1:0] or P1st0[1:0] or P1st1[1:0] ) begin
Casex({Only1[1:0],Exist[1:0]})
4’bxx-x1: P1_0_2nd = P2nd0[1:0];
4’bx0-10: P1_0_2nd = P2nd[1:0] + 4;
4’bx1-10: P1_0_2nd = P1st1[1:0] +4;
4’b00-00: P1_0_2nd = 0;
4’b01-001_0_1st = P1st0[1:0];
4’b10-001_0_1st = P1st1[1:0] + 4;
4’b11-001_0_2nd = P1st1[1:0] + 4;
endcase
end
3． If the timing is tight, we could insert pipeline, At most, we need 4 stage pipeline for calculation, but in 90ns, I think we could reach 800Mhz,

 

[darylz]

always @ (negedge rstn, posedge clk)
begin
if (~rstn) begin
a <= 2'b00;
end
else begin
if (a[0]) begin
a[1] <= a[0];
end
if (i) begin
a[0] <= i;
end
end
end

assign det = & a;

 

[bansalr]

thnkx a lot.