how to design wide bandwidth of LPF in PLL design

[wjwreck]

hello,please help me.
i want design a pll for short switch time(3~5us) in 300MHz frequency step.
How can i do it!?

 

[Avla 0652]

One of the possible ways is to visit www.analog.com
they have a lot of different PLL ICs and proper design tools, pretty simple in use.

AFAIK for fast switching PLL, the Fractional-N PLLs are preferable.
However there is a tradeoff:
Fractional-N PLLs generate worse signal, not so clean as integer-N PLLs.

 

[AdvaRes]

You have to prepare a specification of course after having selecting the types of component that you plan to design.
The heart of the PLL is the VCO, so y'oud better start with this component. Decide which type of VCO you will implement (LC, Ring,...) and the performances to reach.
Once this you can thing of your PLL.

 

[biff44]

300 MHz step size is pretty far. It is unlikely that you PLL will remain in linear mode going from one frequency to the next. I would start off like this:

1) have a DAC that coarse tunes the VCO to almost the right frequency
2) Sum that DAC in with a wideband PLL loop filter I would go for a 1 MHz control loop bandwidth
3) Look carefully at the VCO tuning port. You will want to eliminate almost all of the capacitance to ground on that port. You do not want a lowpass pole formed there.
4) Screw around with the lead/lag parameters of your control loop filter until you have a slightly underdamped loop (a little overshoot).

Then you are done

 

[wjwreck]

One of the possible ways is to visit www.analog.com
they have a lot of different PLL ICs and proper design tools, pretty simple in use.

AFAIK for fast switching PLL, the Fractional-N PLLs are preferable.
However there is a tradeoff:
Fractional-N PLLs generate worse signal, not so clean as integer-N PLLs.

I had thought about the Frac-N PLL,but i am confused about how to design a wide loop band width?eg.5MHz or 10MHz? the pfd is 100MHz or more.

- - - Updated - - -

One of the possible ways is to visit www.analog.com
they have a lot of different PLL ICs and proper design tools, pretty simple in use.

AFAIK for fast switching PLL, the Fractional-N PLLs are preferable.
However there is a tradeoff:
Fractional-N PLLs generate worse signal, not so clean as integer-N PLLs.

I had thought about the Frac-N PLL,but i am confused about how to design a wide loop band width?eg.5MHz or 10MHz? the pfd is 100MHz or more.

- - - Updated - - -

300 MHz step size is pretty far. It is unlikely that you PLL will remain in linear mode going from one frequency to the next. I would start off like this:

1) have a DAC that coarse tunes the VCO to almost the right frequency
2) Sum that DAC in with a wideband PLL loop filter I would go for a 1 MHz control loop bandwidth
3) Look carefully at the VCO tuning port. You will want to eliminate almost all of the capacitance to ground on that port. You do not want a lowpass pole formed there.
4) Screw around with the lead/lag parameters of your control loop filter until you have a slightly underdamped loop (a little overshoot).

Then you are done

if use dac ,the dac noise will make phase noise of the pll bad,how to eliminate? we had thought about it ,but it is difficult to estimate.

 

[biff44]

Maybe you can use a multiplying dac with external voltage source, and then use R-C filters and a stable source to provide low noise. In any event, noise on the DAC will make the VCO move, which the PLL will see and correct. So if it is low frequency noise the PLL will have around 60 dB of open loop gain to correct for it.