How to design the transistor size in this latch?

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Hello everyone,

I am studying the design of frequency divider. I have met a latch architecture shown in the following figure. Does anybody know the name of this type of latch?

What are the advantages of this type of latch over the CML latch?

And How do I size the transistors in the latch?

Can anybody give me some materials about latch design?

Thanks very much!

 
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This is a full swing cross-coupled NMOS latch.

You can learn more about it from this paper:
"AN OVERVIEW OF LOW-VOLTAGE VCO DELAY CELLS AND A WORST-CASE
ANALYSIS OF SUPPLY NOISE SENSITIVITY"
Mohamad El-Hage and Fei Yuan
 
thanks, but how about the latter one, how do i size the trnasistor?
 

The second is a differential latch with resistive load.
Sizing your transistor depends only on the speed requirement. If you'll use this prescaler in PLL you have to pay care also to noise contribution.
 

As a general rule, the control FETs have to be 'stronger' (higher beta) than the cross-coupled FETs so they define the node voltages during current-contention programming
 
thanks,

Can you give me more details about the relationship between speed and transistor size and the noise contribution? Or can you recommend me some papers or books?

Thanks again!

AdvaRes said:
The second is a differential latch with resistive load.
Sizing your transistor depends only on the speed requirement. If you'll use this prescaler in PLL you have to pay care also to noise contribution.
Click to expand...


---------- Post added at 12:55 ---------- Previous post was at 12:44 ----------

unfortunately, I don't have the book! so sad!
oermens said:
Review this book: Model and Design of Bipolar and MOS Current-Mode Logic
Click to expand...
 

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