How to design the reference voltage for high speed ADC?

[zhangjavier]

For pipeline ADC, the reference voltage (Vref_top & Vref_bot) for MDAC operation suffers from the residual input voltage on the sampling cap, which will cause the reference voltage to vary. When the sampling frequency is low, a reference buffer is generally used to settle the reference voltage. When the sampling frequency is high, for example, 200MHz, such buffer is difficult to design and large bypass caps should be used. Such large cap will take large area if implement on-chip. For off-chip implementaion, the parasitic inductor will servely degrade its performance. There seems to be no good method. Does anybody know how to design this reference voltage?

I checked the datasheets of some high speed pipeline ADCs from ADI, NS, Linear,but no detailed explanation.

Thank you.