how to design the filter in all digital pll?

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borislee

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digital pll design

I want to design an all-digital-PLL. The requirement of performance includes the -3dB frequency, the flatness in the passband, etc.
The difficulty now is how to design the digital filter in order to meet the requirement. I have searched in google but got little. Who would like to give me some help?
Thanks in advance!
 

digital pll filter

check the book of roland best there is a chapter about all digital PLL
the book name "PLL Design Simulation and Applications"

u can find it in this link


good luck with ur loop

khouly
 

borislee,

Choose a FIR or IIR filter to design.
Choose a suitable sampling frequency.
Choose the number of taps and coeffcients to determine the frequency response of your digital filter.
Run simulation on Matlab-Simulink and make adjustment of your design.
Implement it either using DSP Processor, FPGA/CPLD or Custom IC.

If you want quick implementation, copy your coefficients done in Mathlab-Simulink and paste it in filter template provided by Texas Instruments TMS320Cxx.

You can also implement in FPGA using VHDL/Verilog template provided by Altera and Xilinx.

Both implementation requires you to run on evaluation kit where ADC and DAC are available on-board.
 

Thanks to khouly & SkyHigh

I think IIR filter is better.
Because I am poor on DSP, I don't know how to convert the requirement of the PLL to the requirement of digital filter. I also have no idea on choosing the coeffcients of the filter.

Implementation on TMS320/FPGA is to check the design. But I don't know how to get the design.

BTW, I never used Matlab. Are there any materials introducing how the simulate the performance of PLL, including -3dB frequency, flatneet in the passbank.
 

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