How to design high voltage regulator?

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legend

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Hi,all,can you tell how to design a linear voltage regulator in high voltage(40V) CMOS process?

thanks.
 

how about your accurate?
u can use sub-pnp as the bandgap or you can use a zener as pre-reg then use bandgap or E-D mos .
 

1. direct use HiV mos + BJT
but as I know some process BJT model have problem is HV

2. use 2 step regulator
40v -> ~12
then use 12v device make bandgap is easy than 40V cmos
40V CMOS L is very large ...
for good Line regulation need Long L


what process in your design 　 UMC/TSMS/VIS or other ??
 

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