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How to design double clocked devices (synthetizable) in VHDL?

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Hi every body,
Please can anyone tell me how to design double clocked devices (synthetizable) in VHDL.
Thanks in advance.
 

Re: Double Clock design

there's a part about that in: A Practical Guide to VHDL Design
it's discussing the pros and cons of double-edge clocking
i didn't find the book here...if someone has a direct link to it for download...i need it as a softcopy
 

Double Clock design

I'll try to find it.

Thanks a Lot Selma, et 3idek mabrouk.

Regards,
Master_PicEngineer.
 

Re: Double Clock design

Salut,

Tu viens de l'Afrique du Nord, n'est ce pas?

Eidak Mabrouk toi aussi

Amicalement,
Salma :D

NB: C'est Salma pas Selma!
 
Double Clock design

Et ben Oui, tu l'as deviné.

Moi je devine de ton nom, que tu est Egyptienne.
Chez nous on prononce Selma. J'ai pas fait attention car lorsque je redige je fait comme si j'était entrain de parler. Je suis vraiment navré.
Je te souhaite 3id mabrouk et kol 3em wenti b5ir.
Comme la tradition l'exige, je t'offre un cadeau pour cet occasion.
(3 point + helped me).

Cordialement,
Master_PicEngineer
 

Re: Double Clock design

Merci beaucoup pour ton cadeau, c'est tres gentil de ta part :D
Tu as bien devine...je suis absolument Egyptienne
C'est pas grave pour ce truc d'orthographe
Pour Eid, je t'envoie des biscuits :)

~~~~BISCUITS~~~~

LOL

Bonne journee,
Salma
 

Double Clock design

ENGLISH PLS................
 

Double Clock design

did you guys find book? if yes, please post it
 

Re: Double Clock design

Hi all..

My dear friend...You cannot check the edge of two clocks for assigning a signal. CAD tools wont allow that.

Thanks
 

Double Clock design

No vlsi_freak,
Synopsys design compiler for exemple support dual clocking.
4 all,
I'm still searching for the book. Please if anybody have the book, share it.

Thanks.
 

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