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hi,
see the book by martin on analog integrated circuit design which has the block diagrams of sigma delta adc and good explanation.decimator can be implemented using vhdl with polyphase architecture.
The simplest decimator it is a counter - first order digital filer+ decimator.
For this case modulator must be also first order. Design is very
simple - 1 OpAmp, 3 capacitors, 1 comparator-latch.
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