how to design a shutdown circuit for LDO

[cc10000]

if 24V input and 5V output for the LDO with 5V/0V enable pin. The DMOS is 5g24d. So how to shut down the LDO totally. Is there any paper or note discussing this topic?

 

[erikl]

If you just want to shut-down Vout -> 0V , it's enough to connect the power transistor's gate with its source - by a transistor switched via the enable/shut-down pin.

Should you need a total 0-current shut down, you'll have to disable some control current, plus, possibly, inactivate some extra enable transistors.

For more detailed info you should show your schematic diagram.

 

[cc10000]

Hi, erikl , thanks so much for ur reply. Maybe i didn't describe my question clearly. I mean for the wide-range input LDO, the enable/disable function realizing is not as easy as the common ones because of the limit of the different ability of withstanding HV between VGS and VDS.if we use the common method, the VGS of the control MOSFET may exceed the highest voltage it can endure. For example MCP1804, it designs a single shutdown block to deal with this issue. I just want to know what is the principle or structure of that such as this block.