cnt_duty_pr : process(clk, rst)
begin
if (rst = '1') then
cnt_duty <= (others => '0');
pwm_out <= '0';
elsif (rising_edge(clk)) then
if (clk_en = '1') then
cnt_duty <= cnt_duty + 1;
end if;
if (cnt_duty < unsigned(duty)) then
pwm_out <= '1';
else
pwm_out <= '0';
Will try it and update!Hi,
most probably you don´t need to divide. (At least I don´t see the question to do so)
if you output 2 pulses HIGH folowed by 6 pulses LOW then everything is done.
.. at least on the VHDL side.
if you are interested in, then you may calculate it...
******
you should draw what you have done so far. anyhow. Maybe as timing diagram (i do this on a checkered sheet) , but you may also do it like this:
lets say [ | ] is a rising clock edge:
then cnt_duty: 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 ...
do you want this?
I can´t write VHDL but can read it a little. I assume there are a couple problems:
* cnt_duty is not defined
* pwm_out is not defined
* clk_en is not defined
* duty is not defined
* "end" is missing
maybe because it´s not finished yet...
...but you are on a good way.
Klaus
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity epwm is port ( clk : in std_logic; reset : in std_logic; d,w: in std_logic_vector(3 downto 0); pulse : out std_logic ); end epwm; architecture rtl_arch of epwm is --signal on1,off1:std_logic_vector(3 downto 0); signal count:std_logic_vector(3 downto 0); begin process(clk,reset) begin if reset = '1' and clk = '1' then pulse<='0'; elsif d>count then pulse<='1'; else pulse<='0'; end if; end process; process(clk,reset) begin if reset='1' and clk='1' then count<="0000"; else count <= std_logic_vector(unsigned(count)+1); end if; end process; end rtl_arch;
if clk'event and clk='1' then
if rst='1' then
Count <= (others => '0');
pulse <= '0';
elsif...
...
end if;
end if;
if rst='1' then
count <= (others => '0');
pulse <= '0';
elsif clk'event and clk='1' then
...
Why if reset = '1' and clk = '1'...?
Are you trying to implement a synchronous reset? If so use:
Code:if clk'event and clk='1' then if rst='1' then Count <= (others => '0'); pulse <= '0'; elsif... ... end if; end if;
If async reset then use:
You might have to be careful with the reset signal though depending on what you are using your PWM for or you might blow something.Code:if rst='1' then count <= (others => '0'); pulse <= '0'; elsif clk'event and clk='1' then ...
Notice that you declared d and w but didn't use w in the code. Why? Is it that it is not needed?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity epwm is port ( clk: in std_logic; reset: in std_logic; d: in std_logic_vector(3 downto 0); w:in std_logic_vector(3 downto 0); pulse: out std_logic); end epwm; architecture rtl_arch of epwm is signal count,count_on,count_off: unsigned(3 downto 0); signal p_n: std_logic; begin process(d,w) begin count_on<= unsigned(d); count_off<=unsigned(w); end process; process(clk,reset) begin if clk'event and clk='1' then if reset='1' then count <="0000"; pulse <= '0'; p_n <='0'; elsif p_n = '0' then if count = count_on -1 then count<="0000"; p_n <= '0'; pulse <= '0'; else count <= count+1; end if; elsif p_n = '0' then if count = count_off-1 then count<="0000"; p_n<='1'; pulse <= '1'; else count <= count+1; end if; end if; end if; end process; end rtl_arch;
specifies the on duration and w off durationWe have asked why you have both D and W as input but you are ignoring us. You need help but you're ignoring the comments of the people you need help from.
Please look at preceding posts on this thread and comment on why you need D and W first.
Also tell us whether it is a homework or not, so we know how to help you.
pulse <= '1' when (count < D) else '0';
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