I need to design POR block which can give immunity to glitch in the power supply.
The requirement is any power supply glitch which losts less than 1us shouldnot trigger the reset pulse. but if the glitch losts for more than 10us then rest pulse should be given..
What is the schematic for this kind of requirement.. How to avoid the big capacitor required to generate the delay..
yea.. how to generate a delay of around 5usec without using high capacitor( not more than 20pF).
I used the Inverter fallowed by Capacitor and a schmitt triger to generate the delay.. but the capacitor was very high.. Is there any other method.. or what is wrong in my simulation..