I need to design a low-voltage to high-voltage level shifter. Is there any recommended ebooks or papers on the designing of low-voltage to high-voltage level shifter? Any recommendations on the architecture for level shifter?
How much high-voltage level shifter we are talking about? If it is in ranges of 5-100volts use a power opamp and if more I suggest you to use a transformer.
I am asking in terms of IC design. The problem with the circuit provided by yeewong_su is that it depends on how low the 1.8V can go. if the 1.8V goes down to 0.8V, the thick-oxide NMOS at the 2.5V portion will not be able to pull the signal low. Is there any other circuits?
This also depends on how fast the signal goes, and how much load needs to be driven. I assume the input is a digital signal while the output is to control analog circuitry. The cross coupled structure can work up to MHz range. If higher speed is needed, may need to cascade a few inverters.
It is quite interesting to read the low-voltage to high voltage level shifter . But I meet a problem. I need to design a 1Gbps to several Gbps PECL output buffer, the traditional source follower's efficiency is too low . Is there any good alternative choice?
What is the speed of your level shifter?
For the frequency under 300MHz for 0.18um CMOS process, you could use the simple circuit with 2 PMOS latch and 2 NMOS .