Mar 17, 2003 #1 E eda_wiz Advanced Member level 2 Joined Nov 7, 2001 Messages 653 Helped 58 Reputation 116 Reaction score 29 Trophy points 1,308 Activity points 6,195 Design Doubt Q. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5. For example: Input Sequence Value Output 1 1 1 0 0 10 2 0 1 101 5 1 0 1010 10 1 1 10101 21 0 Using an FSM to create this
Design Doubt Q. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5. For example: Input Sequence Value Output 1 1 1 0 0 10 2 0 1 101 5 1 0 1010 10 1 1 10101 21 0 Using an FSM to create this