i qoute:
"When the PLL is in lock, Clk1 and Clk2 have identical frequency, but their phase difference can show variations. The PLL will try to maintain a phase difference close to zero, as result of the `ideal integrator' functionality of our low-pass filter. Identical frequency means that between every two edges of Clk1, precisely one edge of Clk2 will occur. After an edge has occurred on both Clk1 and Clk2, both left flip-flops are reset by the nand-gate. Only when two edges occur on Clk1 without an intermediate edge on Clk2, the flip-flop in the cycle slip detector will become set. This can only occur if Clk1 has a higher frequency than Clk2."