reference clock 50K
bandwidth 5KHz(big cap in chip).
N =1000 above
i set the Icp to 5uA, sb tell me the leakage current is so much, and the leakage curren will generate the spur , how to estimate the spur? how to design the PLL with less spur.
the nonideal effects in charge pump produce the spurs, usually harmonious of the compare frequency.the effective means to reduce the spurs is to eliminate or alleviate the nonidealities.
chmhero said:
design a intege N synthesizer.
reference clock 50K
bandwidth 5KHz(big cap in chip).
N =1000 above
i set the Icp to 5uA, sb tell me the leakage current is so much, and the leakage curren will generate the spur , how to estimate the spur? how to design the PLL with less spur.
N=1000 is very large for CPPLL, and the bandwidth is so small that the VCO's noise contribution is too large. CPPLL is not a good solution for such a synthesizer. DDS may be more useful.
sorry ,the PLL is a clock multiplier. like the ADI 9883 or ICS1523.
both two chip have external component(cap and res). i am looking for a idea to t to avoid the external component .