How to design a digital logic with high speed rate

[nemolee]

Dear All,

If you have a high speed design, the speed is up to 400MHz. How to design?

 

[eda_wiz]

keep the combo logic depth low. Use pipelining incase of large paths. use high drive cells....

 

[nand_gates]

I will add this to what whizkid says use BiCMOS logic technology.
All ur state machine should be one hot encoded!

 

[zysmith]

the topic is too vague~~~

 

[quake]

Hi, this question is realy worth debating. by my understanding there are some other techniques for
high speed design, or even custom circuit design and layout. Some techniques used in computational part of DSP and data-path in high speed micro processor can also be used, like re-timing, unfolding,
latch based design, etc.
Anyone who is familiar with this please give some advice, thanks a lot, and others are welcome to go on to talk about this.

 

[carrier]

high speed design need a knowlage about transmition line trantiant.
you can design the PCB of circuit by use this role:
1-er of PCB must be known.
2-data and addrress bus must be 135 degree corner
3-supply must be very low noise
4-lengh of track must be calculated so that the reflection at the end of line do not change the voltage on line.
fo more information study about transmision line.

 

[nand_gates]

If you are talking about ASICs then 400 Mhz is not too high frequency to achive!
We done ASIC for 740Mhz! with tsmc 0.13.

 

[eda_wiz]

If you are talking about ASICs then 400 Mhz is not too high frequency to achive!
We done ASIC for 740Mhz! with tsmc 0.13.

740 Mhz!!! too high...
nand_gates can u tell me which was the application?

 

[nanako]

740MHz, approx 1.35ns between each flip-flop. wonder how many level of logic can you insert in between. even area like sas, sata, pcie, etc whereby data rate is in GHz range, the operating clk for the digitial portion is only functioning at 150MHz max.

 

[quake]

Yes , nand_gates, what is your application?

 

[niuniu]

Woo! do you need to do custom design? synthesis-P&R like flow looks hard to do this job.

 

[power-twq]

1) use anvanced semiconductor manufacture process.

2) divide design into many function block and deal with them carefully.

3) use many stage pipeline architecture.

4) find goog architecture.

5) use physical synthesis.

Dear All,

If you have a high speed design, the speed is up to 400MHz. How to design?