A synthesisable clock multiplier cant be implemented in verilog. well in actuall ckt you can use a 2 i/p xor gate with one input delayed by half (by adding delay buffers) for a x2 clock multiplier
I wonder whether you were thinking of clock dividers?????
if this is home work I cant answer it for you
if you are targeting an FPGA perhaps ..
there are DLL (Delay Lock Loop) modules that you can instantiate
giving 2x 4x etc ... clocks