Re: clock divider
There is no simple response for that question.
Base method is based on series of the d-flop's aech for dividing by factor of two. It is the worst method but sometimes is useful (slow clock or in CPLD's)
If you need fine dividing with precise duty factor you can use Digital Clock Manager block which is included in many types of the FPGA (but not all factors are possible)
In some Xlilinx FPGA each LUT can be used as shift registers. Proper initialization of the shift register as cyclic register with proper initial values for the every bit makes some interesting clock divider with many possible divide and duty factors (and it takes only one LUT per up to divide by 16 factor). This shift registers can be connected together to form bigger divide factors.
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