if you target actual design, you can instantiate Tri-state buffer from the target FPGA and do the required connection. I see a lot of xilinx application do so and do not use HDL description. to avoid different synthesizer methodology.
Tetra:
thank u,when i try it in vhdl,i got the right result,but i still can not do it in verilog,can u say more about "avoid different synthesizer methodology"?