Zerox100 said:if you have DCN on your FPGA it's so easy. Feed the clock to DCM. set DCM shift phase as you wanted and use output clock and a register for shifting.
It's so easy
yes, in fact.omara007 said:Zerox100 said:if you have DCN on your FPGA it's so easy. Feed the clock to DCM. set DCM shift phase as you wanted and use output clock and a register for shifting.
It's so easy
This is just in case that he's desinging for FPGA .. but for ASIC, it's a different story ..
omara007 said:Buffer insertion is not done in the RTL .. this is usually done in the backend .. If you want to simulate your design with the delayed clock at the front-end level, just add a normal non-synthesizable delay in your testbench .. then, when it comes to real implementation, pass the delay information to the backend guys to add the buffer to this clock branch ..
Buffer insertion is well-known for the backend people .. they usually use it as an efficient technique to balance their clock trees ..
shnain said:omara007 said:Buffer insertion is not done in the RTL .. this is usually done in the backend .. If you want to simulate your design with the delayed clock at the front-end level, just add a normal non-synthesizable delay in your testbench .. then, when it comes to real implementation, pass the delay information to the backend guys to add the buffer to this clock branch ..
Buffer insertion is well-known for the backend people .. they usually use it as an efficient technique to balance their clock trees ..
How about post-synthesis STA, how will they know about this delay ?
I believe there is no problem in post-synthesis STA .. it will be the same as pre-synthesis STA .. the only thing is that you are going to use the netlist instead of the rtl .. in both cases, you still don't have the buffers inserted yet ..
salma ali bakr said:well
you can just use delay clauses in your HDL
then in the synthesis, give constraints about this delay
the tool will generate buffers needed to fulfill it
so the post-synthesis simulation would take into account the delay
then in the place and routing, the tool would just throw all the buffers inserted
but will take the same constraints you gave to the synthesis tool
and it'll insert the buffers on its own as needed
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