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In the attached pic, I see the clk signal feeding all the red and blue registers. Is that correct?
In the text you are talking about 2 clock domains. I find the two contradicting.
What if the frequency is not integer multiple of the other? Say Higher frequency is 350MHz and Lower frequency is 80MHz.
Is this a question related to my suggestion about multi-cycle paths?
If so, I think you should accept some over-constraining. With 350 MHz and 4 cycles multi-cycle the blue region will be constrained to 87.5 MHz.
That means theoretically there is a clock_MUX sitting before the clk signal.The clock pin is supplied with two different frequencies depending on which operation is to be performed.
Here is a simplified version of my problem. I have two set of registers as shown. They are operated at different times and there is no path between them. They are clocked by a single clock port. The set of red registers are few in number with not much logic between them and are operated at 320MHz. Blue set of registers are operated at 80MHz.
If I use create_clock on clk port with frequency of 350MHz, the blue set of registers including the large part of clock tree that will never be operated at more than 80MHz gets unnecessarily optimized.
I defined two clocks on the same pin with create_clock, made them physically_exclusive with set_clock_groups and set_false_path between the 350MHz clock and the blue set. But the tool (Genus) still tells there are multiple clock waveforms driving the blue registers (both set). I also tried putting a create_generated_clock with -divide_by 4 on common clock fanout point of the 80MHz domain. The 350MHz constraint is still propogating everywhere.
View attachment 149777
How do I stop the 350MHz clock definition from propagating to the 80MHz domain?
Yes, Sorry.
So I would constrain the primary inputs that are launched with respect to the clock port to the 350MHz clock and set a multi cycle of 4 on them. But the clock tree to the blue registers will still be optimized for 320MHz right?. A slightly different question, I know we have separate clock tree specification file, but will the constraints put in the sdc not affect the clock tree building later?
The clock soirce shown is a direct clk port to the chip. There is no control input for clock selection and it has to be done externally.
Are you sure this thread is SOLVED?The clock soirce shown is a direct clk port to the chip. There is no control input for clock selection and it has to be done externally.
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