I have a top file with the following input and output signal:
INPUTS:
----------
sys_clk
reset
cut 1 bit (if '1', the signal ceases)
start 1 bit (if '1', the design works)
enable 1 bit (if '1', the design and clock is fed to design)
OUTPUTS:
-------------
done 1 bit (end of action flag)
ready 1 bit (ready flag for transmission)
As I looked at the ZedBoard manual in the attachment, the 100 MHz on-board clock signal is on pin Y9, and I want to use DIP switches for cut, start, enable signal (F22, G22, H22) and a push button (BTNC) for reset.
I defied the following constraint in my .XDC file:
where sys_clk is the name of clock signal in my top file that I would like to connect it to pin Y9 to be 100 MHz. But how can I define this constraint in my XDC file? What are the required constraints to be defined for the other signals (DIP switches and push button)??
Kind replies and helps are in advance appreciated.