How to define a synthesizable clock in VHDL TB without wait for statement ???

[asengupt]

Hi,


I saw your replies in the forum and felt encouraged to post this question. Thanks for providing your expertise.

I have a VHDL test bench that is associated with both implementation and simulation (as I would like to run P&R simulation). I just want to define my clock with a certain time period. Say clock = '1', wait for 2.5ns.....clock = '0', wait for 2.5 ns etc

But since my VHDL test bench has "wait for XXX" statement, the code does not compile during synthesis and implementation. I also thought of using loop statement to add delay, but it passes synthesis but fails in translate (error: "xxxx cannot be expanded during NGDbuild"). Pasting the test bench for your reference. Kindly help. Thank you.nnot be expand



LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY check IS
END check;

ARCHITECTURE behavioral OF check IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT test11
PORT(
B : IN std_logic_vector(3 downto 0);
F : IN std_logic_vector(3 downto 0);
Wb : IN std_logic_vector(3 downto 0);
Wc : IN std_logic_vector(3 downto 0);
clock : IN std_logic;
reset : IN std_logic;
Tp : IN std_logic_vector(7 downto 0);
const1 : IN std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;


--Inputs
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal F : std_logic_vector(3 downto 0) := (others => '0');
signal Wb : std_logic_vector(3 downto 0) := (others => '0');
signal Wc : std_logic_vector(3 downto 0) := (others => '0');
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal Tp : std_logic_vector(7 downto 0) := (others => '0');
signal const1 : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal Y : std_logic_vector(7 downto 0);
signal i : integer range 0 to 5;

-- Clock period definitions
--constant clock_period : time := 2.5 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: test11 PORT MAP (
B => B,
F => F,
Wb => Wb,
Wc => Wc,
clock => clock,
reset => reset,
Tp => Tp,
const1 => const1,
Y => Y
);




-- Stimulus process
stim_proc: process
begin

clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;
clock<= '1';
for i in 5 downto 0 loop
end loop;
clock<= '0';
for i in 5 downto 0 loop
end loop;

const1<= "00000001";
F<= "0001";
Tp<= "00001000";
Wb<= "0100";
Wc<= "0001";
B<= "0100";



end process;

END behavioral;

 

[rberek]

Why exactly are you trying to synthesize a testbench? They are for simulation only. You can use them for RTL or gate level simulation, but the testbench remains behavioural code in both cases.

r.b.

 

[TrickyDicky]

In answer to your question - you cant.
And your testbench is completly unsuitable for implementing on an FPGA.
If you want to implement a synthesis testbench, you need to make synthesisable code.