library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
architecture behave of test is
type dataout is array (6 downto 0,11 downto 0) of std_logic;
signal a : dataout := ("000000000000", "000000111111", "101010101010",
"010101010100","111111111111","111111000000","111001100110");
signal b : std_logic;
begin -- behave
process
begin -- process
for i in 0 to 6 loop
for j in 0 to 11 loop
b <= a(i,j);
wait for 5 ns;
end loop; -- j
end loop; -- i
wait;
end process;
end behave;