I have adopted different rules of thumb for each tech I have worked with, more or less. Specifically for the floorplan stage, I would worry about congestion and access to pins first, power distribution. Focus on what those routing channels are looking like. Then you have to figure out if some of your floorplan decisions made timing completely unfeasible. It is usually safe to start with some form of automated floorplan, and then manually improve it to your liking. DRVs will appear at this point, hundreds, or even thousands. Don't worry yet.
Once you are done with that, it is time for placement. You can play with congestion vs timing effort, depending on what you need the most. Placement will take DRV into account if you do OPT at the same time (in cadence lingo that means running place_opt_design). You might still find some DRV violations after placement, but they should be way less than before. Some max_cap violations can occur, some max_tran, even some max_fanout. I wouldn't try to fix all of them before routing and final OPT, but I would make sure I understand where they are coming from. If you have a block that is buried so deep in the floorplan that every wire connecting to it has max_length violations, there is nothing OPT can do for you.