how to decide setup and hold margin on state timing analyze

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feel_on_on

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how to decide setup and hold margin on state timing analyze ？

How much margin can completely assure tapout sucessfully?
 

depends on which stage u are doing STA.
for eg; in prelayout stage 10% margin for setup and 0% hold will do .
 

thanks a lot , But you can assure 10% margin is okay ? if you select another process. then...postlayout stage how much margin I should keep?
 

Re: how to decide setup and hold margin on state timing anal

Well, 10% is not a magic number. I use 15% most of the time. Also, use aggressive wireload model in your early synthesis can take some wiring delay into the synthesis consideration, which will make post-layout timing closure somewhat easier.
 

but ,how to gain 15% ? if you have a bigger margin ,maybe make your design timing is not better?
 

Re: how to decide setup and hold margin on state timing anal

feel_on_on said:
but ,how to gain 15% ? if you have a bigger margin ,maybe make your design timing is not better?
Click to expand...


Set your clock period 15% shorter than your target. Bigger margin may result a little bigger block, but make your backend design easier.
 

So you won't ensure a better margin. only after you have taped out ,you can know if that is enough or too strict.
 

Set your clock period 15% shorter
Click to expand...
Why not to give 15% of setup uncertainly instead? What's the difference?
 

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