How to deal with skew in I2S when master=controller

[tcheung]

In my design, the I2S clock doesn't come from the transmitter nor the receiver, but from a host processor.

The BCLK and LRCLK (or WCLK) is sent from the host processor to both the transmitter and to the receiver. How do I minimize skew in this topology? What do I length-match the dataline to?

Your thoughts?

 

[tcheung]

According to I2S spec, this is the limit that it imposes on the design... but I have yet to understand what it is saying...